1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing the same, and, especially, to a semiconductor device in which a semiconductor chip is mounted on a lead frame.
2. Related Art
Conventionally, semiconductor devices in which semiconductor chips are mounted on a lead frame have been described in Japanese Laid-open patent publication Nos. 62-291156, 5-152503, and 9-283689.
Devices according to Japanese Laid-open patent publication Nos. 62-291156 and 5-152503 among the above documents, have a configuration in which semiconductor chips are installed on both surfaces of a lead frame.
Japanese Laid-open patent publication No. 62-291156 has described that semiconductor chips are installed on both surfaces of a wiring board, and resin sealing is performed for each surface after wire bonding.
Moreover, Japanese Laid-open patent publication No. 5-152503 has described that a plurality of terminal units at locations at different distances from an island unit are provided on the lead frame.
On the other hand, Japanese Laid-open patent publication No. 9-283689 has shown a configuration in which a semiconductor chip is installed on one surface of a lead frame. According to the above configuration, a plurality of semiconductor chips are installed on one surface of a multilayer wiring board, and, at the same time, a lead frame is connected to the wiring board on the back of the surface on which the semiconductor chip is installed.
However, the above-described conventional devices have had room for improvement in flexibility of interconnection design. When specific explanation is made for the above circumstances, a lead frame or a wiring board and a chip are connected to each other by a wire in all the devices according to Japanese Laid-open patent publication Nos. 62-291156, 5-152503, and 9-283689. At this time, it is usual that a conductive member provided on a chip and an external connecting terminal which is adjacent to the above conductive member are connected to each other. Thereby, there have been some cases in which configuration and arrangement for a through path between a chip and an external connecting terminal are limited.